PIC16F877A-I/P【PDF 109/234 页】IC MCU FLASH 8KX14 EE 40DIP

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Sheet目录3827

105页 106页 107页 108页 [109页]110页 111页 112页 113页

2003 Microchip Technology Inc.

DS39582B-page 195

PIC16F87XA

FIGURE 17-19:

A/D CONVERSION TIMING

TABLE 17-15: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

(TOSC/2)(1)

Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP

instruction to be executed.

1 TCY

. . .

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

130

TAD

A/D Clock Period

PIC16F87XA

1.6

—

sTOSC based, VREF ≥ 3.0V

PIC16LF87XA

3.0

—

sTOSC based, VREF ≥ 2.0V

PIC16F87XA

2.0

4.0

6.0

A/D RC mode

PIC16LF87XA

3.0

6.0

9.0

A/D RC mode

131

TCNV

Conversion Time (not including S/H time)

(Note 1)

—12

TAD

132

TACQ

Acquisition Time

(Note 2)

10*

—

The minimum time is the

amplifier settling time. This may

be used if the “new” input volt-

age has not changed by more

than 1 LSb (i.e., 20.0 mV @

5.12V) from the last sampled

voltage (as stated on CHOLD).

134

TGO

Q4 to A/D Clock Start

—

TOSC/2 §

—

If the A/D clock source is

selected as RC, a time of TCY is

added before the A/D clock

starts. This allows the SLEEP

instruction to be executed.

These parameters are characterized but not tested.

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

This specification ensured by design.

Note

ADRES register may be read on the following TCY cycle.

See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.

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